The present invention relates to a programmable integrated circuit having programmable wiring which is programmed freely by a user to achieve his/her desired function element.
There has heretofore been known a programmable integrated circuit having an internal structure capable of programming logic as a kind of data such as a PLD (programmable logic device) using a variety of RAMs, SRAMs, PROMs, EPROMs or EEPROMs.
In such a programmable integrated circuit, programming for writing desired logic is performed by a user to form a desired function element within the integrated circuit. The programming is available in fuse type, electrical erase type and ultraviolet erase type.
FIG. 4 is a schematic diagram illustrating the circuit of an electrically writable programmable integrated circuit for example. In FIG. 4, the integrated circuit includes a programmable logic device 105 (hereinafter referred to as "PLD") such as a SRAM (static random access memory) and furthermore an X-decoder (bit line driver) 101 and Y-decoder (word line driver 103), both for writing programming data. Shift registers for inputting and outputting serial data are used as these decoders. The shift registers for inputting and outputting serial data can be constituted by circuits shown in FIG. 5a. For example, serial data to be inputted into the bit line driver is inputted every bit and shifted in response to the input of a clock signal CLK. To allow the bit line driver 101 to receive serial data equivalent to the number of bit lines, the serial data is inputted into the shift register one by one in response to the clock signals. When the clock signals equivalent to the number of bit lines have been inputted, data input is suspended.
Meanwhile, the word line driver 103 is shifted to a predetermined register in response to the clock signals. In this case, when an enable signal is inputted into both of the bit and word line drivers, data on a bit line in the shift register of the bit line driver 101 is written on the programmable logic element (hereinafter referred to as "PLE") of the PLD 105 at the position of a word line in the shift register of the word line driver 103. For example, as shown in FIG. 5c, data is located in the register at a position n of the bit line driver 101 and in the register at a position m of the word line driver 103, desired logic is inputted into the PLE at an intersection of the both lines of the PLD 105 at the time when a bit line enable signal B-EN agrees with a word line enable signal W-EN.
Likewise, only a predetermined number of new data is read from the shift register of the bit line driver 101 and the shift register of the word line driver 103 is shifted to the word line at a predetermined write position in accordance with reading the new data. Then data located on the bit line is written on the programmable logic device 105 on the word line at a predetermined write position. In this way, programming data is written on the PLD 105.
When the shift register is used as a decoder a described in the foregoing, chip area can be saved and wiring width can be reduced, compared with other input/output means. A programmable integrated circuit having such a structure is described in U.S. Pat. No. 4,870,302 for example.
In the conventional circuit as described in the foregoing, writing (transferring) programming data with the shift register is performed every one-bit. Therefore, even if programming data is received in parallel from the data recorder, programming data is written in series and accordingly, write time is determined by the transfer time of programming data. This transfer speed is particularly important when a test program is executed before programming for setting functions. Test programming is to be performed before programming for setting logic to enable users to construct any circuit through programming. This is an especially important feature of an PLD which programs electrically. This test programming is effected by a program for executing several hundreds of tests such as wiring check. When this test program is executed, processing test programming takes time longer than desired if the speed of data transfer by the aforementioned shift register is low.